Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator

The Non-Von team and our partners at Green Mountain Semiconductor wrote an article on the results of our hardware/software co-design process and the advanced proof of concept chip that resulted.  

    Hokenmeier et al. (2024) IEEE 33rd Microelectronics Design & Test Symposium          (MDTS) doi.org/10.1109/MDTS61600.2024.10570137, https://arxiv.org/pdf/2409.19389​

A logical re-conception of neural networks: Hamiltonian bitwise part-whole architecture

Professor Granger and Dr. Bowen wrote this article on a sparse, compacted network that provided part of the inspiration for development of our novel architecture and software ecosystem. HNet